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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:15:25 04/01/2011 
-- Design Name: 
-- Module Name:    Register_Data_Acc - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Register_Data_Acc is
 Port (    data_in	 	 : in  data_word_type;
           clk_i 		 	 : in  STD_LOGIC;
           clr_i		 	 : in  STD_LOGIC;
           enable_data 	 : in  STD_LOGIC;
           data_out 	 	 : out  data_word_type);
end Register_Data_Acc;

architecture Behavioral of Register_Data_Acc is

begin

process(clr_i, clk_i)
variable data_val: STD_LOGIC_VECTOR (7 downto 0);
begin
	if  rising_edge(clk_i) then--clk = '1' and clk?event then
		if clr_i = '0' then
				data_val := (others => '0'); --este vector lo lleno de 0
		elsif enable_data = '1' then			
			data_val := data_in;
		end if;
	end if;
data_out <= data_val;
end process;

end Behavioral;

